1 application note 1673 authors: don lafontaine, dan goodhew application circuit to generate plus and minus supplies using the isl97701 boost regulator introduction this application note will di scuss a method to combine the operation of a boost regulator and a negative voltage converter. the circuit described will generate both a positive and a negative supply from a single low voltage supply. the circuit in figure 5 shows the standard isl97701 application circuit for a +20v supply along with two isl28107 op amps, two diodes and two capacitors to generate a well regulated -20v supply. understanding the boost topology before we add the additional circ uitry to generate the negative supply, it is important to understand how the boost convertor produces an output voltage that is always greater than the input voltage. in order to do this, we analyze the boost circuits in figure 1 and the current waveforms in figure 2. for this analysis, we account for all the losses in the charging and discharging loops in our equations. this should help to give a complete understanding of the circuit. however, the isl97701?s output voltage is not dependent upon any losses in the circuit. this is because all the losses are inside the circuit?s feedback loop of the isl97701, and are automatically accounted for. the output voltage is defined from the feedback resistor ne twork shown in figure 5 and calculated in equation 1, where v reffb is the internal reference voltage of the isl97701. positive supply figure 1a shows the basic boost converter circuit. during one switching cycle, the transistor q 1 turns on and turns off. during the time q 1 is on, the inductor l 1 is placed in series with the v in supply through the isl97701?s integrated boost fet (q 1 ). the diode d 1 is reversed biased and the circuit reduces to that shown in figure 1b. the voltage across the boost inductor (l 1 ) is equal to v in - (v ds + i l1 x r l1 ) and the current ramps up linearly in inductor l 1 to a peak value at time dt. the peak inductor current ( i l1(on) ) is calculated in equation 3 and shown graphically in figure 1b. any load requirements during this phase are supplied by the output capacitor c 1 . when q 1 turns off, since the current in an inductor cannot change instantaneously, the voltage in l 1 reverses and the circuit becomes that shown in figure 1c. now the no-dot end of l 1 is positive with respect to the dot end and d 1 becomes forward biased. since the dot end is at v in , l 1 delivers its stored energy to c 1 and charges it up to a higher voltage than v in . this energy supplies the load current and replenishes the charge drained away from c 1 . during this time, energy is also supplied to the load from v in . the voltage applied to the dot end of the inductor is (v in - i l1 x r l1 ). the voltage applied to the no-dot end of l 1 is now the output voltage, v o , plus the diode forward voltage v d . the voltage across the inductor during the off-state is ((v o + v d1 + i l1 x r l1 ) - v in ). the inductor current during the off-time of the switch (t-dt) is calculated in equation 4 and shown graphically in figure 1c. in steady-state conditions, th e current increases during the on-time of the switch and decreases during the off-time of the switch, reference figure 2. both on-time and off-time currents are equal to prevent the inductor core from saturating. setting both currents equal to each other and solving for v o results in the continuous conduction mode boost voltage shown in equation 5. v out v reffb r 1 r 2 + () ? r 2 ? = (eq. 1) v out 1.15v r 1 r 2 + () ? r 2 ? = v l l di l dt ------- - i lpk ? v l l ----- - t d t 0 dt == (eq. 2) i l1 on () v in v ds i l1 r l1 + () ? l ------------------------------------------------------------ dt = (eq. 3) figure 1a. figure 1b. figure 1c. figure 1. basic boost topology i l1 off () v o v d1 i l1 r l1 + + () v in ? l ------------------------------------------------------------------------- - tdt ? () = (eq. 4) v o v in i l r l ? 1d ? ------------------------------- - v d1 v ds d 1d ? ------------ - ? ? = (eq. 5) c 1 l 1 v o + - r l r l1 i l1 i o q 1 v in d 1 l 1 + - r l1 i l1 dt iq 1 i l1(on) = (v in -(v ds + i l1 xr l1 ))dt l v in q 1 i q1 v ds 0t c 1 l 1 + - r l r l1 i l1 dt t id v in i l1(off) = (v o +v d +i l1 xr l )-v in (t-dt) d 1 v o l i d caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved. intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. november 18, 2011 an1673.0
application note 1673 2 an1673.0 november 18, 2011 the duty cycle ?d? in equation 5 is determined by setting the losses in equation 5 (i l1 x r l1 , v d1, v ds ) to zero because they are within the feedback loop of the isl97701. the isl97701 varies the duty cycle continuously to keep v o constant, regardless of the conduction losses as a function of load current. with the losses set to zero, equa tion 5 reduces to equation 6. this results in the value for the duty cycle as shown in equation 7. inductor selection the inductor selection determin es the output ripple voltage, transient response, output curren t capability, and efficiency. its selection depends on the input voltage, peak inductor current, output voltage, switching frequency, and maximum output current. when choosing an inductor, make sure the saturation current of the inductor is greater than the i peak of the circuit. likewise, the transistor should be able to handle peak current greater than i peak . the peak inductor current is shown in figure 3 and can be calculated using equation 11. from figure 3, it can be seen that the peak inductor current i l1(pk) is equal to the average inductor current i l1(ave) plus one half the i l1 current, as shown in equation 8. the average power in is equal to the average power out divided by the efficiency of the circuit, as shown in equation 9. where eff is equal to the efficiency of the isl97701 boost regulator. therefore, the average inductor current is equal to the output current times the gain of the boost regulator as shown in equation 10. i l1(on) was defined in equation 3 and the duty cycle ?d? in equation 7. substituting equation 7 into equation 3 and adding it to equation 10 results in equation 11. equation 11 gives the inductor?s peak current in terms of input voltage, output voltage, switching frequency, and maximum output current (again, the losses due to v ds and i l1 x r l1 are not included because they are inside the feedback loop of the isl97701). by rearranging the terms in equations 11, we can solve for the inductor value using equation 12. equation 12 is useful for determining the minimum value of l the circuit can handle withou t exceeding the peak current through the inductor, and therefore, the switch q 1 . the maximum peak current (i peak ) allowed through q 1 for safe operation is given in the electr ical specification table of the isl97701 data sheet as 1.2a. figure 2. inductor, transistor and diode currents i q1 i d1 i l1 ot ot ot dt dt dt t t t q 1 on q 1 off i l1(pk) i l1(ave) i l1 v o v in -------- 1 1d ? ------------ - = (eq. 6) d1 v in v o -------- ? = (eq. 7) figure 3. inductor average and peak currents dt t i l1 i l1(pk) i l1(ave) i l1 o i l1 peak () i l1 ave () 1 2 --- i l1 on () + = (eq. 8) v in i l1 ave () v o i o eff ----------------- - = (eq. 9) i l1 ave () v o i o v in e ff ---------------------- = (eq. 10) i lpeak () v o i o v in e ff ---------------------- 12 ? v in v o v in ? () lv o freq ---------------------------------------- - + = (eq. 11) l v in 2 eff v o v in ? () i pk v in eff i o v o ? () 2v o freq ------------------------------------------------------------------------- - = (eq. 12)
application note 1673 3 an1673.0 november 18, 2011 minimum inductor value design example given: v in = 5v, v o = 25v, i o = 35ma, i pk = 1.2a, freq = 1mhz, eff = 0.85 (efficiency of 85% from figure 3 in isl97701 data sheet). equation 12 gives us the bounda ry condition for the smallest inductor we can have to ensure the peak current through q 1 is less than the max limit of 1.2a. the minimum inductor value for the given conditions is determined to be 2.0h. maintaining ccm design example for maximum efficiency, the boost converter needs to be operated in continuous conduction mode (ccm). to maintain continuous conduction mode oper ation of the boost regulator, the value of i l1(ave) needs to be greater than or equal to i l1 /2, reference figure 3. rearranging terms and solving for l results in equation 15. to maintain continuous conduction mode operation, for the given circuit design conditions above, the value of l has to be greater than 9.71h. it should be noted that when there is a light load, the circuit can slip into discontinuous conduction mode, where the inductor becomes fully discharged of its current each cycle. this operation will reduce the overall efficiency of the supply. using equation 15 and making the value of the inductor large enough for a given minimum output current will insu re continuous conduction mode operation. output capacitor low esr capacitors should be used to minimize the output voltage ripple. multilayer ceramic capacitors (x5r and x7r) are preferred for the output capacitors because of their lower esr and small packages. tantalum capacitors with higher esr can also be used. the output ripple can be calculated in equation 17: for noise sensitive applications, a 0.1f placed in parallel with the larger output capacitor is recommended to reduce the switching noise. negative supply the operation of the negative supply is best understood by considering figure 5. we will start our analysis under steady state conditions (the inductor op erating in continuous conduction mode and c 1 is equal to the voltage calculated in equation 1). when q 1 turns off, the inductor voltage flies up turning on d 1 and d 3 . diode d 2 is blocking current flow from c 3 . the inductor current now charges both capacitors c 1 and c 2 with the polarity as shown in figure 5. the voltage on c 2 is equal to the voltage on c 1 , plus the forward voltage drop of d 1 . when q 1 turns on, diodes d 1 and d 3 are blocking and capacitor c 2 is now in parallel with capacitor c 3 through d 2 (which is now on), reference figure 4. this connection results in a negative voltage being transferred on to c 3 . the voltage transferred to c 3 is equal to the voltage on c 1 as shown in figure 4 and equation 18. the efficiency of the charge transfer between the two capacitors is related to the energy lost during this process. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs . the energy lost is defined in equation 19: where v 1 and v 2 are the voltages on c 2 during the charging and transfer cycles. if the impedances of c 2 and c 3 are relatively high at the 1mhz frequency compared to the value of r l , there will be substantial difference in the voltages v 1 and v 2 . therefore, it is not only desirable to make c 3 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 2 in order to achieve maximum efficiency of operation. output voltage regulation using op amps the final output voltage regulation is accomplished using two isl28107 op amps (note: two separate op amps required because of the different supply connections). the voltage developed by the boost converter powers the amplifiers and the output voltage is calculated using equations 20 and 21. l 5v () 2 0.85 () 25 5 ? () 1.2a 5 () 0.85 () 35ma 25 () ? () 225 () 1mhz ------------------------------------------------------------------------------------------------------------ - 2.0 h == (eq. 13) i l1 ave () 1 2 --- i l1 (eq. 14) v o i o v in e ff ---------------------- 12 ? v in v o v in ? () lv o freq ---------------------------------------- - l12 ? v in v o v in ? () v o i o v in e ff ---------------------- v o freq --------------------------------------------------------- - (eq. 15) l12 ? 5v 25v 5v ? () 25v 35ma 5v 0.85 () --------------------------------- 25v 1mhz ------------------------------------------------------------------------- 9.71 h ? (eq. 16) v o i out d f sw c 1 ---------------------- - i out esr + = (eq. 17) figure 4. charging of negative supply capacitor c 3 v c3 c 2 d 1 v c1 d 2 + - + + - - v = v c1 +d 1 c 3 c 1 q 1 turns on connecting c 2 to ground as shown. v c1 d 1 + () d 2 ? v c3 ? 0 = (eq. 18) v c1 v c3 = e 1 2 --- c 2 v 1 2 v 2 2 ? () = (eq. 19) (eq. 20) v out positive () 5v r 3 r 4 + () ? r 3 ? = (eq. 21) v out negative () v out positive () ? r 6 ? r 5 ? =
application note 1673 4 intersil corporation reserves the right to make changes in circuit design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1673.0 november 18, 2011 restriction on design: 1. for reasonable voltage regulation of the negative supply voltage, the negative supply current needs to be less than or equal to the positive supply current. this is because the control loop for output voltage regulation is around the positive supply voltage only. 2. the maximum output current of the circuit shown in figure 5 is limited by the maximum output current of the isl28107 op amps, which is 40ma. 3. the isl97701 is optimized to work best for a small range of inductors. the slope compensati on ramp generator, inside the isl97701, is optimized for inductor values between the range of 4.7h to 15h and output currents between 25ma to 125ma. the circuit will work for inductor values outside this range, as long as the maximum i peak current is not exceeded (equation 12). the only drawback will be a reduction in the efficiency of the circuit. the percent efficiency could drop from the 80?s to the 60?s as the operation goes from continuous conduction mode to discontinuous conduction mo de. reference the isl97701 data sheet for additional info rmation on performance of the boost regulator. 4. to obtain output currents hi gher than 40ma, the user could: ? operate the circuit without the op amps (at the cost of output voltage regulation) by connecting directly to c 1 and c 3 ? or replace the op amps with ones with higher output current drive capability 5. the accuracy of the output volt age is highly dependent on the input voltage source. using a well regulated voltage source is recommended. (eq. 22) i out positive () i out negative () figure 5. reference design to genera te a positive and negative supply oscillator and control vddout nen nsync gnd c 0 5f c 1 4.7f r 1 383k r 2 18.2k l 1 10h lx vout fb 25.35v vdd 5v c 3 4.7f + + - - r 6 100k r 5 100k 5v c 2 4.7f - 25.35v r 4 100k r 3 33.2k d 1 q 1 v 0 d 2 d 3 + - + + - - vout (positive) 20v vout (negative) -20v isl97701 isl28107 isl28107 5v v- v- v+ v+
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